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ISL23345 bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp

tên linh kiện ISL23345
Giải thích chi tiết về linh kiện  Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
PDF  19 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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ISL23345 bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp

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ISL23345
FN7872 Rev 0.00
Page 13 of 19
June 21, 2011
Functional Pin Descriptions
Potentiometers Pins
RHI AND RLI
The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals
of the ISL23345 are equivalent to the fixed terminals of a
mechanical potentiometer. RHi and RLi are referenced to the
relative position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be closest
to RHi, and with the WRi set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
VCC
Power terminal for the potentiometer section analog power source.
Can be any value needed to support the voltage range of the DCP
pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, wiper address and data
from an I2C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FIGURE 23. 10k
 -3dB CUT OFF FREQUENCY
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
1V/DIV
0.2µs/DIV
WIPER
SCL
0.5V/DIV
20µs/DIV
VCC
WIPER
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.437MHz AT MIDDLE TAP
CH1: RH TERMINAL
CH2: RW TERMINAL
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-40
-15
10
35
60
85
110
VCC = 1.7V, VLOGIC = 1.2V
VCC = 5.5V, VLOGIC = 5.5V
TEMPERATURE (°C)



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