9.1.2 Capacitive Transducer Input Stage

Piezoelectric transducers are used for many different applications that require low-noise, high-gain performance.

These transducers exhibit high output impedance (> 10 MΩ), and therefore require very high impedance loading

for subsequent input stages. The JFE150 has ultra-low input gate current (maximum IG = ±10 pA) and low

input capacitance (CISS = 24 pF), which makes the device an excellent choice for transducers with an effective

capacitance of greater than 240 pF. For smaller, lower-capacitance transducers, the CISS can impact the gain of

the front end by attenuating the input signal, thereby reducing the noise performance.

9.1.3 Common-Source Amplifier

The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers. Figure 9-2 shows

the basic circuit.

V

+

JFE150

V

IN

R

D

R

S

+

±

+

±

+

±

RG

VOUT

Figure 9-2. Common-Source Amplifier

Equation 1 shows the equation for gain of the circuit in Figure 9-2.

VOUTVIN= −  gm*RD

1+gm*RS

(1)

Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased

as a result of increasing gm (see Figure 6-4). As a result, the input-referred noise decreases as bias current

is increased (see Figure 6-9). Any JFET design must make a tradeoff between current consumption and

noise performance. The JFE150, however, delivers significantly lower noise performance than most operational

amplifiers at the same current consumption. The bias current (IDS) is set by the value of the source resistor, RS,

and the threshold voltage, VT, of the JFE150. Figure 9-3 is a graph showing nominal IDS vs RS.

Figure 9-3. Drain-to-Source Current vs RS, VDS = 5 V

JFE150

SLPS732B – JUNE 2021 – REVISED APRIL 2023

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