MPC9993 REVISION 3 JANUARY 23, 2013

4

©2013 Integrated Device Technology, Inc.

MPC9993 Data Sheet

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS) PLL CLOCK DRIVER

Table 4. DC Characteristics (VCC = 3.3 V ± 5%, TA = – 40° to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset)

VIH

Input High Voltage

2.0

VCC + 0.3

V

VIL

Input Low Voltage

0.8

V

IIN

Input Current(1)

1. Inputs have internal pull-up/pull-down resistors affecting the input current.

100

A

VIN = VCC or GND

LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad)

VOH

Output High Voltage

2.0

V

IOH = –24 mA

VOL

Output Low Voltage

0.55

V

IOL = 24 mA

LVPECL clock inputs (CLK0, CLK1, Ext_FB)(2)

2. Clock inputs driven by differential LVPECL compatible signals.

VPP

DC Differential Input Voltage(3)

3. VPP is the minimum differential input voltage swing required to maintain AC characteristics.

0.1

1.3

V

Differential operation

VCMR

Differential Cross Point Voltage(4)

4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)

range and the input swing lies within the VPP (DC) specification.

VCC –1.8

VCC –0.3

V

Differential operation

IIN

Input Current(1)

100

A

VIN = VCC or GND

LVPECL clock outputs (QA[1:0], QB[2:0])

VOH

Output High Voltage

VCC –1.20

VCC –0.95

VCC –0.70

V

Termination 50

 to VTT

VOL

Output Low Voltage

VCC –1.90

VCC –1.75

VCC –1.45

V

Termination 50

 to VTT

Supply Current

IGND

Maximum Power Supply Current

180

mA

GND Pins

ICC_PLL

Maximum PLL Supply Current

15

mA

VCC_PLL Pin