MPC96877

558

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

RECOMMENDED FILTERING FOR THE ANALOG POWER SUPPLY (AVDD)

Figure 13. AVDD Filtering

NOTES:

1. Place the 2200pF capacitor close to the PLL

2. Use a wide trace for the PLL analog power and ground. Connect

PLL and caps to AGND to AGND trace & connect trace to one GND

via (farthest from PLL).

3. Recommended bead: Fair Rite P/N 2506036017Y0 or equivalent

(0.8 Ohm DC max, 600 Ohms @ 100 MHz)

GND

CARD

VIA

Bead

0603

AVDD

1 ohm

R1

R1

AGND

VDDQ

4.7 uF

1206

4.7 uF

1206

4.7 uF

1206

PLL

MPC96877

1.8 V PLL 1:10 Differential SDRAM Clock Driver

NETCOM

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC96877

12