MPC962305 REVISION 8 3/15/16

4

©2016 Integrated Device Technology, Inc.

MPC962305 Data Sheet

LOW-COST, 3.3V ZERO DELAY BUFFEr

Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices(1)

1. All parameters are specified with loaded outputs.

Parameter

Name

Test Conditions

Min

Typ

Max

Unit

t1

Output Frequency

30-pF load

10-pF load

10

10

100

133.33

MHz

MHz

Duty Cycle(2) = t2 t1

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Measured at 1.4 V, FOUT = 66.67 MHz

40.0

50.0

60.0

%

t3

Rise Time(2)

Measured between 0.8 V and 2.0 V

2.50

ns

t4

Fall Time(2)

Measured between 0.8 V and 2.0 V

2.50

ns

t5

Output to Output Skew(2)

All outputs equally loaded

250

ps

t6A

Delay, REF Rising Edge to

CLKOUT Rising Edge(2)

Measured at VDD/2

0

350

ps

t6B

Delay, REF Rising Edge to

CLKOUT Rising Edge(2)

Measured at VDD/2. Measured in PLL Bypass Mode,

MPC962309 device only

15

8.7

ns

t7

Device to Device Skew(2)

Measured at VDD/2 on the CLKOUT pins of devices

0

700

ps

tJ

Cycle to Cycle Jitter(2)

Measured at 66.67 MHz, loaded outputs

200

ps

tLOCK

PLL Lock Time(2)

Stable power supply, valid clock presented on REF pin

1.0

ms

Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices(1)

1. All parameters are specified with loaded outputs.

Parameter

Name

Test Conditions

Min

Typ

Max

Unit

t1

Output Frequency

30-pF load

10-pF load

10

10

100

133.33

MHz

MHz

Duty Cycle(2) = t2

t1

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Measured at 1.4 V, FOUT = 66.67 MHz

40.0

50.0

60.0

%

Duty Cycle(2) = t2

t1

Measured at 1.4 V, FOUT < 50 MHz

45.0

55.0

55.0

%

t3

Rise Time(2)

Measured between 0.8 V and 2.0 V

1.50

ns

t4

Fall Time(2)

Measured between 0.8 V and 2.0 V

1.50

ns

t5

Output to Output Skew(2)

All outputs equally loaded

250

ps

t6A

Delay, REF Rising Edge to

CLKOUT Rising Edge(2)

Measured at VDD/2

0

350

ps

t6B

Delay, REF Rising Edge to

CLKOUT Rising Edge(2)

Measured at VDD/2. Measured in PLL Bypass Mode,

MPC962309 device only

15

8.7

ns

t7

Device to Device Skew(2)

Measured at VDD/2 on the CLKOUT pins of devices

0

700

ps

t8

Output Slew Rate(2)

Measured between 0.8 V and 2.0 V using Test Circuit #2

1

V/ns

tJ

Cycle to Cycle Jitter(2)

Measured at 66.67 MHz, loaded outputs

200

ps

tLOCK

PLL Lock Time(2)

Stable power supply, valid clock presented on REF pin

1.0

ms