MPC94551 REVISION 4 3/15/16

3

©2016 Integrated Device Technology, Inc.

MPC94551 Data Sheet

Low Voltage 1:4 CMOS Clock Buffer

Table 1. Pin Description

Pin Number

Pin Name

Pin Type

Pin Description

1

ICLK

Input

Clock input, internal pull-up resistor

2

Q1

Output

Clock output(1)

1. A 33

 series terminating resistor may be used on each clock output if the trace is longer than 1 inch.

3

Q2

Output

Clock output(1)

4

Q3

Output

Clock output(1)

5

Q4

Output

Clock output(1)

6

GND

Power

Connect to ground(2)

2. A decoupling capacitor of 0.01

F should be connected between V

DD on pin 7 and GND on pin 6, as close to the device as possible.

7VDD

Power

Connect to 3.3 V(2)

8

OE

Input

Output enable, tri-states outputs when low, internal pull-up resistor

Table 2. Absolute Maximum Ratings(1)

1. Stresses above the ratings listed below can cause permanent damage to the device. These ratings are stress ratings only. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed

only over the recommended operating temperature range.

Parameter

Rating

Unit

Power Supply Voltage, VDD

3.9

V

All Inputs and Outputs

–0.5 to VDD +0.5

V

Ambient Operating Temperature

–40 to +85

°C

Storage Temperature

–65 to +150

°C

Junction Temperature

175

°C

Soldering Temperature

260

°C

Table 3. DC Characteristics (VDD = 3.3 V ± 5%; Ambient Temperature = –40°C to 85°C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating Voltage

VDD

3.15

3.45

V

Input High Voltage(1), ICLK

1.

Nominal switching threshold is VDD/2.

VIH

VDD/2 + 0.7

3.8

V

Input Low Voltage(1), ICLK

VIL

VDD/2 – 0.7

V

Input High Voltage, OE

VIH

2VDD

V

Input Low Voltage, OE

VIL

0.8

V

Ouput Low Voltage

VOL

IOL = 12 mA

0.4

V

Output High Voltage

VOH

IOH = –12 mA

2.4

V

Operating Supply Current

IDD

No load, 135 MHz

30

mA

Nominal Output Impedance

ZO

27



Internal Pull-up Resistor

RPU

ICLK

31

k



Input Capacitance

CIN

OE pin

5

pF

CIN

ICLK

1

pF

Short Circuit Current

IOS

±50

mA

L

h X 45˚

θ

C

SEATING

PLANE

S

B

M

0.25

A S

C

B

A1

C

A

0.10

1

4

5

8

M

B

M

0.25

D

E

H

A

B

e

DIM

MIN

MAX

MILLIMETERS

A

1.35

1.75

A1

0.10

0.25

B

0.35

0.49

C

0.19

0.25

D

4.80

5.00

E

1.27 BSC

e

3.80

4.00

H

5.80

6.20

h

0˚

7˚

L

0.40

1.25

θ

0.25

0.50

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.

3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

D/EF SUFFIX

SOIC PACKAGE

CASE 751-06

ISSUE T

PACKAGE DIMENSIONS