DATA SHEET

3.3V 1:12 LVCMOS PLL Clock Generator

MPC9772

MPC9772 REVISION 8 3/16/16

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©2016 Integrated Device Technology, Inc.

The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted

for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With output

frequencies up to 240 MHz and output skews less than 250 ps the device meets

the needs of the most demanding clock applications.

Features

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1:12 PLL Based Low-Voltage Clock Generator

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3.3 V Power Supply

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Internal Power-On Reset

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Generates Cock Signals Up to 240 MHz

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Maximum Output Skew of 250 ps

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On-Chip Crystal Oscillator Clock Reference

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Two LVCMOS PLL Reference Clock Inputs

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External PLL Feedback Supports Zero-Delay Capability

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Various Feedback and Output Dividers (See Applications Information

Section)

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Supports Up to Three Individual Generated Output Clock Frequencies

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Synchronous Output Clock Stop Circuitry for Each Individual Output for

Power Down Support

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Drives Up to 24 Clock Lines

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Ambient Temperature Range 0

C to +70C

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Pin and Function Compatible To the MPC972

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52-Lead Pb-Free Package

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For drop in replacement use 87972DYI-147

Functional Description

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as

well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the

feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference

versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-

tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-

binary factor. The MPC9772 also supports the 180

 phase shift of one of its output banks with respect to the other output banks.

The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-

tem baseline timing signals.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-

acteristics do not apply.

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

MPC9772. The MPC9772 has an internal power-on reset.

The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

 transmission

lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an

effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.

3.3 V 1:12 LVCMOS

PLL CLOCK GENERATOR

AE SUFFIX

52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 848D-03

MPC9772

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016