MPC9653 REVISION 4 FEBRUARY 4, 2013

3

©2013 Integrated Device Technology, Inc.

MPC9653 Data Sheet

3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR

Table 1. Pin Configurations

Number

Name

Type

Description

PCLK, PCLK

Input

LVPECL

PECL reference clock signal

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to QFB

VCO_SEL

Input

LVCMOS

Operating frequency range select

BYPASS

Input

LVCMOS

PLL and output divider bypass select

PLL_EN

Input

LVCMOS

PLL enable/disable

MR/OE

Input

LVCMOS

Output enable/disable (high-impedance tristate) and device reset

Q0-7

Output

LVCMOS

Clock outputs

QFB

Output

LVCMOS

Clock output for PLL feedback, connect to FB_IN

GND

Supply

Ground

Negative power supply (GND)

VCC_PLL

Supply

VCC

PLL positive power supply (analog power supply). It is recommended to use an external RC

filter for the analog power supply pin VCC_PLL. Please see APPLICATIONS INFORMATION

for details.

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation

Table 2. Function Table

Control

Default

0

1

PLL_EN

1

Test mode with PLL bypassed. The reference clock

(PCLK) is substituted for the internal VCO output.

MPC9653 is fully static and no minimum frequency limit

applies. All PLL related AC characteristics are not

applicable.

Selects the VCO output(1)

1. PLL operation requires BYPASS = 1 and PLL_EN = 1.

BYPASS

1

Test mode with PLL and output dividers bypassed. The

reference clock (PCLK) is directly routed to the outputs.

MPC9653 is fully static and no minimum frequency limit

applies. All PLL related AC characteristics are not

applicable.

Selects the output dividers.

VCO_SEL

1

VCO

 1 (High frequency range). fREF = fQ0–7 = 4  fVCO

VCO

 2 (Low output range). fREF = fQ0–7 = 8  fVCO

MR/OE

0

Outputs enabled (active)

Outputs disabled (high-impedance state) and reset of the

device. During reset the PLL feedback loop is open. The

VCO is tied to its lowest frequency. The length of the reset

pulse should be greater than one reference clock cycle

(PCLK).

Table 3. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VTT

Output Termination Voltage

VCC  2

V

MM

ESD Protection (Machine Model)

200

V

HBM

ESD Protection (Human Body Model)

2000

V

LU

Latch-Up Immunity

200

mA

CPD

Power Dissipation Capacitance

10

pF

Per output

CIN

Input Capacitance

4.0

pF

Inputs