MPC93R51 datasheet(10/14 Pages) RENESAS

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MPC93R51

REVISION 4 MARCH 14, 2016

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Figure 8. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines, the

situation in Figure 9 should be used. In this case, the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance, the line

impedance is perfectly matched.

Figure 9. Optimized Dual Line Termination

Figure 10. CLK MPC93R51 AC Test Reference for VCC = 3.3 V

Figure 11. PCLK MPC9R351 AC Test Reference

TIME (ns)

3.0

2.5

2.0

1.5

1.0

0.5

OutB

tD = 3.9386

OutA

tD = 3.8956



MPC93R51

OUTPUT

BUFFER

RS = 22

ZO = 50

RS = 22

ZO = 50

+ 22  || 22  = 50  || 50 

 = 25 

Pulse

Generator

Z = 50



RT = 50

ZO = 50

RT = 50

ZO = 50

MPC93R51 DUT

VTT

Differential Pulse

Generator

Z = 50



RT = 50

ZO = 50

RT = 50

ZO = 50

MPC93R51 DUT

VTT

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