HSP45314

FN4820 Rev 3.00

Page 13 of 14

Jan 2001

33, 34

PH(1:0)

Input

Phase Offset Bits. The phase of the output is shifted. If not used, these pins should be grounded.

00 – 0 degrees reference

01 – 90 degrees shift

10 – 180 degrees shift

11 – 270 degrees shift

4

ENOFR

Input

Enable Offset Frequency. Active High. When high, the offset frequency bus is enabled to the

phase accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the

contents of the offset frequency registers. If not used, the pin should be grounded.

10

COMPOUT

Output

Comparator Output.

11

REFLO

Input

Connect to analog ground to enable the DAC’s internal 1.2V reference or connect to AVDD to

disable the internal reference.

12

REFIO

Input

Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a

0.1

F cap to ground from the REFIO pin when a DC reference voltage is used.

13

FSADJ

Full Scale Current Adjust for the DAC. Use a resistor to ground (RSET) to adjust the full scale

output current. Full Scale Output Current = 32 x VFSADJ/RSET, where VFSADJ equals the

reference voltage.

14

COMP1

Noise reduction for the DAC. Connect a 0.1

F cap to AVDD plane.

19

COMP2

Noise reduction for the DAC. Connect a 0.1

F cap to AGND plane.

18

IOUTA

Output

DAC Current Output.

17

IOUTB

Output

DAC Complementary Current Output.

20

AVDD

Power

Analog Supply Voltage.

15, 16, 21, 24

AGND

Gnd

Analog Ground.

7, 26, 31, 43

DVDD

Power

Digital Supply Voltage.

5, 25, 28, 29, 41

DGND

Gnd

Digital Ground.

22, 23

IN+, IN-

Input

Comparator Inputs. To power down the comparator, connect both of these pins to the analog

power supply. This will conserve ~4mA of current.

39

NC

NC

No Connect.

Control Register Descriptions

ADDRESS

BITS

DESCRIPTION

RESET

STATE

0

7:0

Center frequency bits CF(7:0) (Least Significant Byte).

00 h

1

7:0

Center frequency bits CF(15:8).

00 h

2

7:0

Center frequency bits CF(23:16).

00 h

3

7:0

Center frequency bits CF(31:24).

00 h

4

7:0

Center frequency bits CF(39:32).

00 h

5

7:0

Center frequency bits CF(47:40) (MSByte). (Reset gives

fCLK/4 output).

40 h

6

7:0

Offset frequency bits OF(7:0) (LSByte).

00 h

7

7:0

Offset frequency bits OF(15:8).

00 h

8

7:0

Offset frequency bits OF(23:16).

00 h

9

7:0

Offset frequency bits OF(31:24).

00 h

10

7:0

Offset frequency bits OF(39:32).

00 h

11

7:0

Offset frequency bits OF(47:40) (MSByte).

00 h

Pin Descriptions (Continued)

PIN NO.

PIN NAME

TYPE

PIN DESCRIPTION