9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure

optimal performance. This can be accomplished by providing short, appropriately sized traces from the

SN74HCS273 to one or more of the receiving devices.

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

Q1

D1

CLK

CLR

Figure 9-2. Application Timing Diagram, One Data Channel Shown

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SN74HCS273

SCLS851D – MARCH 2021 – REVISED JANUARY 2023

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