10

ICSSSTUB32866B

Advance Information

1165A—3/21/07

2. Device standard (cont'd)

†

‡

CK

D1•D25 †

RST

tsu

tpd

CK to PPO

th

tsu

th

tpdm , t pdmss

CK to Q

DCS

CSR

CK

Q1•Q25

PAR_IN †

nn + 1

n + 2

PPO

n + 3

n + 4

tPHL

CK to QERR

QERR ‡

tPHL , t PLH

CK to QERR

tact

H, L, or X

H or L

Data to QERR Latency

After RST is switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t

max, to avoid false error.

If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on

the n+3 clock pulse.

ACT

Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;

RST Switches from L to H