874208I Data Sheet

LVDS CLOCK DIVIDER AND FANOUT BUFFER

REVISION A 9/18/14

2

©2014 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1,

32

ADR1,

ADR0

Input

Pulldown

I2C Address inputs. LVCMOS/LVTTL compatible interface levels.

2, 7, 18, 23

GND

Power

Power supply ground.

3, 4

Q0, nQ0

Output

Differential output pair 0. LVDS interface levels.

5, 6

Q1, nQ1

Output

Differential output pair 1. LVDS interface levels.

8, 17

VDDO

Power

Output power supply pins.

9, 10

Q2, nQ2

Output

Differential output pair 2. LVDS interface levels.

11, 12

Q3, nQ3

Output

Differential output pair 3. LVDS interface levels.

13, 14

Q4, nQ4

Output

Differential output pair 4. LVDS interface levels.

15, 16

Q5, nQ5

Output

Differential output pair 5. LVDS interface levels.

19, 20

Q6, nQ6

Output

Differential output pair 6. LVDS interface levels.

21, 22

Q7, nQ7

Output

Differential output pair 7. LVDS interface levels.

24, 25

FSEL0,

FSEL1

Input

Pulldown

Frequency divider select controls. See Table 3A for function.

LVCMOS/LVTTL interface levels.

26

IN

Input

Non-inverting differential clock input.

27

VT

Termination

input

Input for termination. Both IN and nIN inputs are internally terminated 50

 to

this pin. See input termination information in the applications section.

28

nIN

Input

Inverting differential clock input.

29

VDD

Power

Power supply pins.

30

SDA

I/O

Pullup

I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels.

Output: open drain.

31

SCL

Input

Pullup

I2C clock input. LVCMOS/LVTTL compatible interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4

pF

RPULLDOWN

Input Pulldown Resistor

51

k



RPULLUP

Input Pullup Resistor

51

k

