ICS854110AKI REVISION B JANUARY 27, 2011

3

©2011 Integrated Device Technology, Inc.

ICS854110I Data Sheet

2.5V DIFFERENTIAL LVDS CLOCK BUFFER

Function Tables

Table 3A. CLK_SEL Configuration Table

NOTE: CLK_SEL is an asynchronous control.

Table 3B. nOE Configuration Table

NOTE: OE is an asynchronous control.

Table 3C. RSET Configuration Table

NOTE: The RSET resistor at the ISET pin allows configuration of the

outputs to one of four pre-set output slew rates. A 5% variation of the

RSET resistor size will be tolerated.

NOTE: Slew rates are defined as ±100mV from the center of Q – nQ

signal.

Table 3D. Guaranteed Input Fail Safe Operations for CLK0, nCLK0 and CLK1, nCLK1

Input

Operation

CLK_SEL

0

CLK0, nCLK0 is the selected reference clock

1

CLK1, nCLK1 is the selected reference clock

Input

Operation

nOE

0

Outputs Qx, nQx are enabled.

1

Outputs Qx, nQx are in high-impedance state.

RSET

Typical Output Slew Rate (V/ns)

Resistor Size (k

Ω)

4

0.650 (fastest)

15

0.170

50

0.150

150

0.115 (slowest)

Input State of Selected Input

Outputs Q[0:9], nQ[0:9]

Logic Low (Selected Input: CLKx = LOW, nCLKx = HIGH)

Logic Low (Qx = LOW, nQx = HIGH)

Logic High (Selected Input: CLKx = HIGH, nCLKx = LOW)

Logic High (Qx = HIGH, nQx = LOW)

Inputs Open (Selected Input: CLKx = open, nCLKx = open)

Logic High (Qx = HIGH, nQx = LOW)

Inputs Shorted (Selected Input: CLKx shorted to nCLKx and tied to VDD)

Logic High (Qx = HIGH, nQx = LOW)

Input Shorted (Selected Input: CLKx shorted to nCLKx and floating)

Logic High (Qx = HIGH, nQx = LOW)