HIP0045

FN4047 Rev 12.00

Page 2 of 10

Apr 1999

Detailed Block Diagram

Input to Output Control Tables

OUT2-5

DRIVER

VCC

OC

REF

VREF

ISK

-

+

-

+

Q

S

R

Q2 - 5

ON/OFF

LATCH

DIAG2-5

STATUS

OUT6, 7

DRIVER

VCC

OC

REF

VREF

ISK

-

+

-

+

Q

S

R

Q6, 7

ON/OFF

LATCH

DIAG6, 7

STATUS

OVER-TEMP.

DET.

OUT0, 1

DRIVER

VCC

OC

REF

VREF

ISK

-

+

Q

S

R

OVERLOAD LATCH

VCC

IN 0, 1

Q0, 1

ON/OFF

SCK

MOSI

8-BIT

OUTPUT

LATCH

Q0-7

DIAG 0-7

MISO

D

Q

RESET

LOW

VOTAGE

RESET

RESET

CE

VCC

SPI

SHIFT

REG

OUT

IN

VCC

VCC

VCC

NOTES:

1. OC = Over-Current Voltage Ref. = 1.8V Typ.

2. ISK = Current Sink Pull-Down = 500A Typ.

3. Diag0, 1 = Status bit when Q0, 1 controlling OUT0, 1.

4. Diag0, 1 = Fault bit when IN1, 0 controlling OUT0, 1.

5. Refer to text and Tables 6, 7 for diagnostic information.

STATUS/

FAULT LATCH

FILTER

FAULT

RESET

FILTER

RESET

Q

S

R

DIAG 0, 1

OVERLOAD LATCH

OVERLOAD LATCH

LATCH

-

+

TABLE 1. OUTPUT 0

SPI BIT 0

IN0

OUT0

01

OFF

00

ON

10

ON

11

ON

TABLE 2. OUTPUT 1

SPI BIT 1

IN1

OUT1

01

OFF

00

ON

10

ON

11

ON

TABLE 3. OUTPUT 2 - 7

SPI BIT 2 - 7

OUT2 - 7

0OFF

1ON

TABLE 4. OUTPUT CONTROL REGISTER, Q0 - 7

Q1

Q3

Q5

Q7

Q0

Q2

Q4

Q6

(D7I)

(D6I)

(D5I)

(D4I)

(D3I)

(D2I)

(D1I)

(D0I)

MSB

LSB

NOTE: The Output Control Register bits Q0 -7 have the same order

as the Diagnostic Failure Register bits Diag0 - 7 as defined in

Table 5. Data bits D0I - D7I give the MOSI SPI serial data input flow

sequence.