DSPIC30F datasheet(162/248 Pages) MICROCHIP

162 / 248 page

dsPIC30F

DS70083G-page 160

Preliminary

 2004 Microchip Technology Inc.

20.3.1

POR: POWER-ON RESET

A power-on event will generate an internal POR pulse

when a V

DD rise is detected. The Reset pulse will occur

at the POR circuit threshold voltage (V

POR) which is

nominally 1.85V. The device supply voltage character-

istics must meet specified starting voltage and rise rate

requirements. The POR pulse will reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the oscil-

lator configuration fuses.

The POR circuit inserts a small delay, T

POR, which is

nominally 10

µs and ensures that the device bias cir-

cuits are stable. Furthermore, a user selected power-

up time-out (T

PWRT) is applied. The TPWRT parameter

is based on device configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at

device power-up, T

POR + TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock and the PC will jump to the

Reset vector.

The timing for the SYSRST signal is shown in

Figure 20-3 through Figure 20-5.

FIGURE 20-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 20-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

PWRT

OST

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

PWRT

OST

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

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