DSPIC30F datasheet(30/248 Pages) MICROCHIP

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dsPIC30F

DS70083G-page 28

Preliminary

 2004 Microchip Technology Inc.

2.5

DSP Engine

Concurrent operation of the DSP engine with MCU

instruction flow is not possible, though both the MCU

ALU and DSP engine resources may be used concur-

rently by the same instruction (e.g., ED and EDAC

instructions).

The DSP engine consists of a high speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

Data input to the DSP engine is derived from one of the

following:

Directly from the W array (registers W4, W5, W6

or W7) via the X and Y data buses for the MAC

class of instructions (MAC,

MSC,

MPY,

MPY.N, ED, EDAC, CLR

and MOVSAC).

From the X bus for all other DSP instructions.

From the X bus for all MCU instructions which

use the barrel shifter.

Data output from the DSP engine is written to one of the

following:

The target accumulator, as defined by the DSP

instruction being executed.

The X bus for MAC, MSC, CLR and MOVSAC

accumulator writes, where the EA is derived

from W13 only. (MPY, MPY.N, ED and EDAC

do not offer an accumulator write option.)

The X bus for all MCU instructions which use the

barrel shifter.

The DSP engine also has the capability to perform

inherent

accumulator-to-accumulator

operations,

which require no additional data. These instructions are

ADD, SUB

and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

Fractional or integer DSP multiply (IF).

Signed or unsigned DSP multiply (US).

Conventional or convergent rounding (RND).

Automatic saturation on/off for AccA (SATA).

Automatic saturation on/off for AccB (SATB).

Automatic saturation on/off for writes to data

memory (SATDW).

Accumulator

Saturation

mode

selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-9.

Note:

For CORCON layout, see Table 4-3.

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