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M95M02-DFMN6P/KF bảng dữ liệu(PDF) 15 Page - STMicroelectronics

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M95M02-DFMN6P/KF bảng dữ liệu(HTML) 15 Page - STMicroelectronics

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6.3.4
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The
status register write disable (SRWD) bit and write protect (W) signal enable the device to be put in the hardware
protected mode (when the status register write disable (SRWD) bit is set to 1, and write protect (W) is driven low).
In this mode, the non-volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write
status register (WRSR) instruction is no longer accepted for execution.
Figure 11. Status register format
SRWD
Status register write
protect
0
0
BP0
0
WEL
WIP
BP1
b7
b6
b2
b0
b5
b1
b4
b3
Write in progress bit
Write enable latch bit
Block protect bits
M95M02-DR M95M02-DF
Read status register (RDSR)
DS7024 - Rev 13
page 15/45



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