ADM1185

Preliminary Technical Data

Rev. PrK | Page 8 of 12

OUT1

OUT2

OUT3

2.5V OUT

1.8V OUT

PWRGD

VIN4

VIN2

VIN3

POWER

GOOD

EN

Regulator1

3.3V IN

EN

OUT

IN

2.5V OUT

EN

OUT

IN

1.8V OUT

OUT

IN

GND

1.2V OUT

1.2V OUT

Regulator2

Regulator3

VCC

VIN1

ADM1185

Figure 5. Applications Diagram showing ADM1185 in a voltage monitoring and sequencing application

State1

IN1=FAULT

IN1=OK

(Delay=100ms min)

IN1=FAULT

IN1=FAULT

IN1=FAULT

Start

State2

State3

State4

State5

OUT1

On

IN2=OK

IN3=OK

IN4=OK

(Delay=100ms min)

OUT1,2

On

OUT1,2,3

On

PWRGD

IN2.IN3.IN3=FAULT

Figure 6. Flow Diagram highlighting the different modes of operation o the logical core

State

State Name

OUT1

OUT2

OUT3

OUT4

Next Event

Next State

1

Reset*

0

0

0

0

IN1 High for 190ms

Out1 On

2

Out1 On

1

0

0

0

IN1 and IN2 High for 30us

Out1,2 On

3

Out1,2 On

1

1

0

0

IN1 and IN3 High for 30us

Out1,2,3 On

4

Out1,2,3 On

1

1

1

0

All High for 190ms

PowerGood

IN2 or IN3 or IN4 Low for

30us

Out1,2,3 On

5

PowerGood

1

1

1

1

IN1 Low for 30 us

Start

Table 4. Truth table