CCG1401 Datasheet

Feb 28, 2022

Page 13

7. FUNCTION DESCRIPTION

SPI and Digital Control

A synchronous serial interface receives data from an external controller via DIO, CLK and CSX. This interface

consists of a 10-bit shift register, 2-bit header and 8 bit data. Each positive slope at CLK shifts the value at DIO

into the shift register. With a positive slope at CSX the 8 data bits of the shift register are transferred to the address

register or a parameter register depending on the value of the header. A data package with header “00” selects a

parameter register. Following data packages with

header “01” are intended for the previously selected register.

To read out the registers content, the header needs to be “10”. DIO changes then its functionality from input to

output and DIO pin has to be released. Data can be shifted out with the positive edge of CLK. Sampling of data

should occur on the negative edge. Maximum frequency when reading is 50 kHz. The output data starts with the

register content at address 0, followed by the one at address 1 and ends with the content of register 4. After

transfer of the last bit, when CSX goes high, DIO changes its functionality back to input behavior. The DIO-

behavior is visualized by the internal signal DOUT_EN in the timing diagram. Standby modus of analog circuitry

can be selected by register (see 0) and alternatively by setting CSX=High and CLK=High. The SPI is not affected

by standby operation. The comparator threshold can be controlled by register content and setting DIO=High for

using the register SREF1 (see 5.4.4) or setting DIO=Low for using register SREF2 (see 5.4.5). Take into

consideration that this mechanism does not work during an SPI-transfer.

SPI Timing

Figure 4: Timing Diagram