85310I-21 Data Sheet

©2016 Integrated Device Technology, Inc

June 24, 2016

2

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

Number

Name

Type

Description

1V

CC

Power

Core supply pin.

2, 5

nc

Unused

No connect.

3

CLKA

Input

Pulldown Non-inverting differential clock input.

4

nCLKA

Input

Pullup

Inverting differential clock input.

6

CLKB

Input

Pulldown Non-inverting differential clock input.

7

nCLKB

Input

Pullup

Inverting differential clock input.

8V

EE

Power

Negative supply pin.

9, 16, 25, 32

V

CCO

Power

Output supply pins.

10, 11

nQB4, QB4

Output

Differential output pair. LVPECL interface levels.

12, 13

nQB3, QB3

Output

Differential output pair. LVPECL interface levels.

14, 15

nQB2, QB2

Output

Differential output pair. LVPECL interface levels.

17, 18

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

19, 20

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

21, 22

nQA4, QA4

Output

Differential output pair. LVPECL interface levels.

23, 24

nQA3, QA3

Output

Differential output pair. LVPECL interface levels.

26, 27

nQA2, QA2

Output

Differential output pair. LVPECL interface levels.

28, 29

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

30, 31

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

TABLE 3. CLOCK INPUT FUNCTION TABLE

Inputs

Outputs

Input to Output Mode

Polarity

CLKA or CLKB

nCLKA or nCLKB

QA0:QA4,

QB0:QB4

nQA0:nQA4,

nQB0:nQB4

0

1

LOW

HIGH

Differential to Differential

Non Inverting

1

0

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential

Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential

Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information, “Wiring the Differential Input to Accept Single Ended Levels”.