CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

84427 DATA SHEET

2

REVISION B 5/6/15

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

Number

Name

Type

Description

1, 2

Q0, nQ0

Output

Differential output pair. LVDS interface levels.

3, 4

Q1, nQ1

Output

Differential output pair. LVDS interface levels.

5, 6

Q2, nQ2

Output

Differential output pair. LVDS interface levels.

7, 8

Q3, nQ3

Output

Differential output pair. LVDS interface levels.

9, 10

Q4, nQ4

Output

Differential output pair. LVDS interface levels.

11, 12

Q5, nQ5

Output

Differential output pair. LVDS interface levels.

13, 16, 24

V

DD

Power

Core supply pins.

14

GND

Power supply ground.

15

PLL_SEL

Input

Pullup

Selects between the PLL and crystal inputs as the input to the dividers.

When HIGH, selects PLL. When LOW, selects XTAL_IN and XTAL_OUT.

LVCMOS / LVTTL interface levels.

17

V

DDA

Power

Analog supply pin.

18

F_SEL2

Input

Pullup

Feedback frequency select pin. LVCMOS/LVTTL interface levels.

19,

20

XTAL_OUT,

XTAL_IN

Input

Crystal oscillator interface. XTAL_IN is the input,

XTAL_OUT is the output.

21

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs Qx to go low and the inverted outputs nQx

to go high. When logic LOW, the internal dividers and the outputs are

enabled. LVCMOS / LVTTL interface levels.

22

F_SEL1

Input

Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels.

23

F_SEL0

Input

Pullup

Output frequency select pin. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.