84329B DATA SHEET

REVISION B 07/29/14

6

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

Table 4C. LVPECL DC Characteristics, VCC =VCCA = 3.3V±5%, TA = 0°C to 70°C

NOTE 1: Outputs terminated with 50

 to V

CC –2V.

Table 5. Crystal Characteristics

Table 6. Input Frequency Characteristics, VCC =VCCA = 3.3V±5%, TA = 0°C to 70°C

NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz or

700MHz. Using the minimum input frequency of 10MHz, valid values of M are 400

 M  511. Using the maximum input frequency of 25MHz,

valid values of M are 160

 M  448.

AC Electrical Characteristics

Table 7. AC Characteristics, VCC =VCCA = 3.3V±5%, TA = 0°C to 70°C

See Parameter Measurement Information section.

Characterized using 16MHz XTAL.

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: See Applications Section.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

VOH

Output High Current; NOTE 1

VCC – 1.4

VCC – 0.9

µA

VOL

Output Low Current; NOTE 1

VCC – 2.0

VCC – 1.7

µA

VSWING

Peak-to-Peak

Output Voltage Swing

0.6

1.0

V

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

10

25

MHz

Equivalent Series Resistance (ESR)

50



Shunt Capacitance

7pF

Drive Level

1mW

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fIN

Input

Frequency

XTAL; NOTE 1

10

25

MHz

S_CLOCK

50

MHz

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

700

MHz

tjit(per)

Period Jitter, RMS;

NOTE 1, 2

fOUT  65MHz

5.5

ps

fOUT < 65MHz

12

ps

tjit(cc)

Cycle-to-Cycle Jitter;

NOTE 1, 2

fOUT  50MHz

35

ps

fOUT < 50MHz

50

ps

tR /tF

Output Rise/Fall Time

20% to 80%

300

800

ps

tS

Setup Time

5

ns

tH

Hold Time

5

ns

odc

Output Duty Cycle

45

50

55

%

tLOCK

PLL Lock Time

10

ms