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87LPC767 bảng dữ liệu(PDF) 9 Page - NXP Semiconductors |
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87LPC767 bảng dữ liệu(HTML) 9 Page - NXP Semiconductors |
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9 / 60 page  Philips Semiconductors Product data 87LPC767 Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter 2001 Aug 07 6 P2.0–P2.1 6, 7 I/O Port 2: Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 2 also provides various special functions as described below. 7 O P2.0 X2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. 6 I P2.1 X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). VSS 5 I Ground: 0 V reference. VDD 15 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes. SPECIAL FUNCTION REGISTERS Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0h 00h C7 C6 C5 C4 C3 C2 C1 C0 ADCON#* A/D Control C0h ENADC – – ADCI ADCS RCCLK AADR1 AADR0 00h AUXR1# Auxiliary Function Register A2h KBF BOD BOI LPEP SRST 0 – DPS 02h1 F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0h 00h CMP1# Comparator 1 control register ACh – – CE1 CP1 CN1 OE1 CO1 CMF1 00h1 CMP2# Comparator 2 control register ADh – – CE2 CP2 CN2 OE2 CO2 CMF2 00h1 DAC0# A/D Result C5h 00h DIVM# CPU clock divide-by-M control 95h 00h DPTR: Data pointer (2 bytes) DPH Data pointer high byte 83h 00h DPL Data pointer low byte 82h 00h CF CE CD CC CB CA C9 C8 I2CFG#* I2C configuration register C8h/RD SLAVEN MASTRQ 0 TIRUN – – CT1 CT0 00h1 C8h/WR SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0 DF DE DD DC DB DA D9 D8 I2CON#* I2C control register D8h/RD RDAT ATN DRDY ARL STR STP MASTER – 80h1 D8h/WR CXA IDLE CDR CARL CSTR CSTP XSTR XSTP I2DAT# I2C data register D9h/RD RDAT 0 0 0 0 0 0 0 80h D9h/WR XDAT x x x x x x x AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8h EA EWD EBO ES ET1 EX1 ET0 EX0 00h EF EE ED EC EB EA E9 E8 IEN1#* Interrupt enable 1 E8h ETI – EC1 EAD – EC2 EKB EI2 00h1 BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8h – PWD PBO PS PT1 PX1 PT0 PX0 00h1 IP0H# Interrupt priority 0 high byte B7h – PWDH PBOH PSH PT1H PX1H PT0H PX0H 00h1 |
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