PES8NT2 datasheet(2/29 Pages) RENESAS

2 / 29 page

2 of 28

January 5, 2009

IDT 89HPES8NT2 Data Sheet

◆

Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC pass-through

– Supports Hot-Swap

◆

Power Management

– Supports PCI Power Management Interface specification,

Revision 1.1 (PCI-PM)

– Unused SerDes are disabled

◆

Testability and Debug Features

– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator

– Ability to read and write any internal register via the SMBus

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

◆

Two SMBus Interfaces

– Slave interface provides full access to all software-visible

registers by an external SMBus master

– Master interface provides connection for an optional serial

EEPROM used for initialization

– Master and slave interfaces may be tied together so the switch

can act as both master and slave

◆

Eight General Purpose Input/Output pins

◆

Packaged in 19x19mm 324 ball BGA with 1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES8NT2 provides

the most efficient high-performance I/O connectivity solution for applica-

tions requiring high throughput, low latency, and simple board layout

with a minimum number of board layers. With support for non-trans-

parent bridging, the PES8NT2 is part of the IDT PCIe System Intercon-

nect Products that target multi-host and intelligent I/O applications

requiring inter-domain communication. The PES8NT2 provides 32 Gbps

(4 GBps) of aggregated, full-duplex switching capacity through 8 inte-

grated serial lanes, using proven and robust IDT technology. Each lane

provides 2.5 Gbps of bandwidth in both directions and is fully compliant

with PCI Express Base specification 1.0a.

The PES8NT2 is based on a flexible and efficient layered architec-

ture. The PCI Express layer consists of SerDes, Physical, Data Link,

and Transaction layers in compliance with PCI Express Base specifica-

tion Revision 1.0a. The PES8NT2 can operate either as a store and

forward or cut-through switch depending on the packet size and is

designed to switch memory and I/O transactions. It supports eight Traffic

Classes (TCs) and one Virtual Channel (VC) with sophisticated resource

management.

Switch Configuration

The PES8NT2 is a two port switch that contains eight PCI Express

lanes. Each of the two ports is statically allocated eight lanes with ports

labeled as A and C. Port A is the upstream port and port C is the non-

transparent downstream port.

During link training, link width is automatically negotiated. Each

PES8NT2 port is capable of independently negotiating to a x4, x2, or x1

width. Thus, the PES8NT2 may be used in virtually any two port switch

configuration (e.g., {x4, x4}, {x4, x2}, {x2, x2}, etc.). The PES8NT2

supports static lane reversal. For example, lane reversal for upstream

port A may be configured by asserting the PCI Express Port A Lane

Reverse (PEALREV) input signal or through serial EEPROM or SMBus

initialization. Lane reversal for port C may be enabled via a configura-

tion space register, serial EEPROM, or the SMBus.

PES8NT2 bảng dữ liệu(PDF) 2 Page - Renesas Technology Corp

PES8NT2 bảng dữ liệu(HTML) 2 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

bảng dữ liệu tải về

Link URL