F1978 Datasheet

© 2017 Integrated Device Technology, Inc.

13

Rev O August 28, 2017

Conventional Serial Mode Programming

In the Conventional Serial Mode, the F1978 is programmed via the serial port on the rising edge of the Latch Enable (LE) signal. It is required

that LE be kept at logic LOW until all data bits are clocked into the shift register. The F1978 will change its attenuation state after the data word

is latched into the active register as illustrated in Figure 18. After the data word in the shift register has been latched into the active register, the

LE signal must be dropped LOW. This allows shifting new data into the shift register without uploading it to the active register until the next time

LE goes HIGH. The timing specification intervals are shown in blue font in Figure 18.

Figure 18. Conventional Serial Register Timing Diagram

Note: If the Conventional Serial Register programming method is used, the attenuator will change to the new attenuation state only after the

data word is latched into the active register, a single programming event. The Conventional Serial Register method is recommended for best

system performance.

Table 9.

Conventional Serial Mode Timing Table

Interval Symbol

Description

Min Spec

Max Spec

Units

tmc

Parallel Mode to Serial Mode setup time: from the rising edge of VMODE

to the rising edge of CLK for the D5 bit

100

ns

tds

Clock HIGH pulse width

10

ns

tcls

LE setup time: from the rising edge of the CLK pulse for D0 to LE rising

edge minus half the clock period

10

ns

tclh

LE hold time: from the falling edge of the LE pulse to the rising edge of

CLK

10

ns

tlew

LE pulse width

10

ns

tdcs

Data setup time: from the starting edge of the data bit to the rising edge

of CLK

10

ns

tdht

Data hold time: from rising edge of CLK to falling edge of the data bit

10

ns