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DA6021 bảng dữ liệu(PDF) 69 Page - Renesas Technology Corp |
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DA6021 bảng dữ liệu(HTML) 69 Page - Renesas Technology Corp |
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69 / 225 page ![]() DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 69 of 224 www.dialog-semiconductor.com Voltage Rail Control Mechanism 11.4 Proper power-up/down sequencing is mandatory preventing damages. Optimizing the platform power consumption, unneccessary components as well as its related power rails shall be switched off. There are several methods controlling the power rails. VCC & VNN are controlled via the SVID interface State transitions, SOC provides SLP_S0iX_B, SLP_S3_B and SLP_S4_B signals to DA6021 controlling the related power rails Sequencer controlling Dedicated register control SVID Interface 11.5 SOC communicates with the DA6021 via the SVID interface. SVID‘s commands composed of 9 bits – 4 MSBs determine the address and 5 LSBs are the command bits. DA6021 supports 2 SVID voltage regulators – VCC & VNN. The address for each of the voltage regulator is indicated in the table below: Address Target Description 0x00 VCC All commands will be routed to the VCC SVID registers and DA6021 will respond with the VCC status information 0x01 VNN All commands will be routed to the VNN SVID registers and DA6021 will respond with the VNN status information Table 30: VCC & VNN Addresses SVID DC Electrical Parameters 11.5.1 The following table outlines the SVID DC electrical parameters. Note that low voltage operation is essential to avoid level converters to/from the processor. DA6021 SVID buffer should take V1P0S_FB as a reference voltage for improved signal integrity at the receiver. Symbol Parameter Min Typ Max Units Notes Val V1P0S SVID IO voltage 0.95 1.00 1.05 V - VIL Input low voltage 0.45* V1P0S V 1 A VIH Input high voltage 0.65* V1P0S V 1 A VHYS Hysteresis voltage 0.05 V E,D VOH Output high voltage V1P0S V 1 - RON Buffer on resistance (data line & alert# line) 10 20 Ω 2 D IL Leakage current -100 100 uA 3 A CPAD Pad capacitance 4.0 pF 4 D VPIN Pin capacitance 5.0 pF D Table 31: SVID DC Electrical Characteristics |
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