6

Application information

6.1

Turn-on and soft startup feature

When the input voltage is applied, the En/Fault pin goes up to the high state and the internal control circuitry is

enabled.

After an initial delay time of typically 250 µs, the output voltage is ramped up with a slope defined by the internal

dv/dt circuitry. If no additional capacitor is connected to dV/dt pin, the ramp-up time (VOUT from 10% to 90%) is

around 0.85 ms.

Connecting a capacitor between the Cdv/dt pin and GND allows the modification of the output voltage ramp-up

time. Given the desired time interval Δt during which the output voltage goes from zero to its maximum value, the

capacitance to be added on the Cdv/dt pin can be calculated using the following theoretical formula.

Δt ms =0.85+Cdv/dtpF ×0.021

Figure 5. Delay time and VOUT ramp-up time

0

2

4

6

8

10

12

Time

En/Fault

Vout

delay

time

ramp-up

time

90%

10%

Table 6. Rise time vs. Cdvdt

Cdvdt (pF)

0

22

33

47

100

180

270

470

1000

Rise time

(ms)

0.85

1.3

1.56

1.9

3

4.7

6.6

11

22

6.2

Maximum load at startup

Depending on supply voltage and load, it is possible that during startup the power dissipation is such that the

maximum power protection is triggered and the output is shut down before the startup is complete. The EN/Fault

signal is set according to Figure 6. En/Fault pin status. En/Fault pin behavior during thermal protection events.

In case of strong capacitive loads, the total start-up time may be longer than the programmed start-up time, since

it is dependent also on the limitation current, the output load and the output capacitance value. In such a situation,

the foldback current limit could activate, so that the startup is longer or interrupted by the intervention of thermal

protection. To avoid this occurrence, a longer start-up time should be set by the appropriate selection of the Cdv/dt

capacitor.

6.3

Normal operating conditions

The STEF12S eFuse behaves like a mechanical fuse, supplying the circuitry on its output with the same voltage

shown on its input, with a small voltage fall due to the internal N-channel MOSFET RDS(on).

STEF12S

Application information

DS13002 - Rev 5

page 8/31