4

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDTCSPT855

2.5V PLL CLOCK DRIVER

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Commercial: TA = 0°C to +70°C; Industrial: TA = –40°C to +85°C

Symbol

Parameter

Conditions

Min.

Typ.(1)

Max.

Unit

VIK

Input Voltage (All Inputs)

VDDQ = 2.3V, II = -18mA

—

—

– 1.2

V

VOH

HIGH-Level Output Voltage

VDDQ = Min. to Max., IOH = -1mA

VDDQ – 0.1

—

—

V

VDDQ = 2.3V, IOH = -12mA

1.7

—

—

VOL

LOW-Level Output Voltage

VDDQ = Min. to Max., IOL = 1mA

—

—

0.1

V

VDDQ = 2.3V, IOL = 12mA

—

—

0.6

IOH

HIGH-Level Output Current

VDDQ = 2.3V, VO = 1V

– 18

– 32

—

mA

IOL

LOW-Level Output Current

VDDQ = 2.3V, VO = 1.2V

26

35

—

mA

VOD

Output Voltage Swing

Differentialoutputsareterminatedwith120

Ω

1.1

—

VDDQ – 0.4

V

VOX

Output Differential Cross Voltage(2)

Differentialoutputsareterminatedwith120

Ω

VDDQ/2 – 0.2

VDDQ/2

VDDQ/2 + 0.2

V

II

InputCurrent

VDDQ = 2.7V, VI = 0V to 2.7V

—

—

±10

μA

IOZ

High-ImpedanceStateOutputCurrent

VDDQ = 2.7V, VO = VDDQ or GND

—

—

±10

μA

IDD(PD)

Power-Down Current on VDDQ and AVDD

CLK and

CLK = 0MHz, PWRDWN = LOW,

—

100

200

μA

Σ of IDD and AIDD

IDD

Dynamic Current on VDDQ

CL = 14pF

fO = 167MHz, Differential outputs terminated with 120

Ω

—

150

180

mA

CL = 0pF

fO = 167MHz, Differential outputs terminated with 120

Ω

—

130

160

AIDD

Supply Current on AVDD

fO = 167MHz

—

8

10

mA

CI

InputCapacitance

VDDQ = 2.5V, VI = VDDQ or GND

2

2.5

3

pF

CO

OutputCapacitance

VDDQ = 2.5V, VI = VDDQ or GND

2.5

3

3.5

pF

NOTES:

1. All typical values are at respective nominal VDDQ.

2. Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.

TIMING REQUIREMENTS

Symbol

Parameter

Min.

Max.

Unit

fCLK

Operating Clock Frequency

60

220

MHz

tDC

Input Clock Duty Cycle

40

60

%

tL

Stabilization Time (PLL Mode)(1)

—10

μs

tL

Stabilization Time (Bypass Mode)(2)

—30

ns

NOTES:

1. Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND).

2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference

signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are

not applicable. This parameter does not apply for input modulation under SSC application.