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80KSW0002 bảng dữ liệu(PDF) 18 Page - Renesas Technology Corp |
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80KSW0002 bảng dữ liệu(HTML) 18 Page - Renesas Technology Corp |
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18 / 48 page ![]() IDT80KSW0002 Datasheet CPS-16 Datasheet 47 April 6, 2016 At recommended operating conditions with VDD3 = 2.5V ± 100mV Table 13 IRQ Electrical Specifications (VDD3 = 2.5V ± 100mV) Figure 13 IRQ Timing Diagram The IRQ pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. The IRQ pin goes active low when any special error filter error flag is set, and is cleared when all error flags are reset. Please refer to the device user’s manual for full detail. 15 Serial RapidIO Ports Overview The CPS-16’s SERDES are in full compliance to the RapidIO AC specifications for the LP-Serial physical layer [5]. This section provides those specifications for reference. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud. Two transmitter specifications allow for solutions ranging from simple chip-to-chip interconnect to driving two connectors across a backplane. A single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. The short run transmitter setting should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power used by the transceivers. The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive signals across two connectors and a backplane. The CPS-16 can drive beyond the specification distance of at least 50 cm at all baud rates. Please use IDT’s Simulation Kit IO models to determine reach and signal quality for a given PCB design. Parameter Symbol Min Max Unit Low level output voltage (IOL = 2mA, VDD3 = Min.) VOL 0 0.4 V Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10pF to 400pF tOF - 25 ns Input current each I/O pin (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (max)) II -10 10 uA Capacitance for IRQ CI - 10 pF |
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