AT45DB641E datasheet(44/69 Pages) RENESAS

44 / 69 page

AT45DB641E

DS-45DB641E-027N–DFLASH–2/2022

16.

Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) will be in a high

impedance state, and a high-to-low transition on the CSB pin will be required to start a valid instruction. The SPI mode

(Mode 3 or Mode 0) will be automatically selected on every falling edge of CSB by sampling the inactive clock state.

16.1

Power-Up/Power-Down Voltage and Timing Requirements

During power-up, the device must not be READ for at least the minimum t

VCSL time after the supply voltage reaches the

minimum V

POR level (VPOR min). While the device is being powered-up, the internal Power-On Reset (POR) circuitry

keeps the device in a reset mode until the supply voltage rises above the minimum V

cc. During this time, all operations

are disabled and the device will not respond to any commands.

If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum V

CC level and an internal device delay has elapsed. This delay will

be a maximum time of t

PUW. After the tPUW time, the device will be in the standby mode if CSB is at logic high or active

mode if CSB is at logic low. For the case of Power-down then Power-up operation, or if a power interruption occurs (such

that VCC drops below VPOR max), the Vcc of the Flash device must be maintained below VPWD for at least the minimum

specified T

PWD time. This is to ensure the Flash device will reset properly after a power interruption.

Table 16-1. Voltage and Timing Requirements for Power-Up/Power-Down

Figure 16-1. Power-Up Timing

Symbol

Parameter

Min

Max

Units

PWD

(1)

Not 100% tested (value guaranteed by design and characterization).

CC for device initialization

1.0

PWD

(1)

Minimum duration for device initialization

300

µs

VCSL

Minimum V

CC to chip select low time for Read command

µs

(1)

CC rise time

500000

µs/V

POR

Power on reset voltage

1.45

1.6

PUW

Power up delay time before Program or Erase is allowed

VCC

POR max

Max V

PWD

Chip Select Not Permitted

Time

PWD

PUW

Full Operation Permitted

VCSL

Read Operation

Permitted

AT45DB641E bảng dữ liệu(PDF) 44 Page - Renesas Technology Corp

AT45DB641E bảng dữ liệu(HTML) 44 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

bảng dữ liệu tải về

Link URL