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ALED7709ATR bảng dữ liệu(PDF) 39 Page - STMicroelectronics

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8.2.2
Start and Stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 20, a START condition
is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition
of the SDA line while SCL is HIGH.
START and STOP are conditions always generated by master; after a START the bus is considered busy and
becomes free again a certain time after STOP. For this reason, a STOP condition must be sent at the end of each
communication.
A second START condition sent before a STOP condition is called Repeated START (or RESTART) and it is
normally used to change the communication direction, typically from Write to Read.
Figure 20. Start and Stop on the I2C bus
8.2.3
Byte format
Every packet transferred on the SDA line must contain eight bits, each byte is followed by an acknowledge bit.
Each clock pulse transfers a single bit of the packet, the data transfer is MSB (Most Significant Bit) first.
The level on the SDA line must remain stable during the HIGH period of the clock pulse, any change in the SDA
line at this time is considered as a control signal (START or STOP condition).
Figure 21. Bit transfer
8.2.4
Acknowledge (ACK) and not acknowledge (NACK)
After every byte the acknowledge take place, this allows the receiver to inform the transmitter if the byte was
successfully received and another byte can be sent or if the transmission failed. It is a duty of the master to
generate all the needed clock pulses, including the acknowledge ninth pulse.
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse so the receiver can force and
keep LOW the SDA line during this clock pulse (see Figure 22).
If the receiver left HIGH the SDA line during the ninth clock pulse, it generates the so called Not Acknowledge
signal. In this case, the master can generate either a STOP condition to abort the transfer, or a Repeated START
condition to initiate a new transfer.
ALED7709
I2C serial bus
DS14214 - Rev 1
page 39/63



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