List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 2

Figure 3.

Operational timing diagram ........................................................... 7

Figure 4.

Serial timing diagram................................................................ 7

Figure 5.

SCLK and CS timing parameters ....................................................... 7

Figure 6.

DNL vs. output codes (AVCC = DVCC = 3 V) ............................................... 8

Figure 7.

DNL vs. output codes (AVCC = DVCC = 5 V) ............................................... 8

Figure 8.

INL vs. output codes (AVCC = DVCC = 3 V) ................................................ 8

Figure 9.

INL vs. output codes (AVCC = DVCC = 5 V) ................................................ 8

Figure 10.

+/- DNL vs. AVCC = DVCC ........................................................... 8

Figure 11.

+/- INL vs. AVCC = DVCC ............................................................ 8

Figure 12.

SNR vs. AVCC = DVCC.............................................................. 9

Figure 13.

THD vs. AVCC = DVCC .............................................................. 9

Figure 14.

ENOB vs. AVCC = DVCC ............................................................ 9

Figure 15.

+/- DNL vs. DVCC with AVCC = 5 V ..................................................... 9

Figure 16.

+/- INL vs. DVCC with AVCC = 5 V ...................................................... 9

Figure 17.

+/- DNL vs. SCLK duty cycle .......................................................... 9

Figure 18.

+/- INL vs. SCLK duty cycle .......................................................... 10

Figure 19.

SNR vs. SCLK duty cycle............................................................ 10

Figure 20.

THD vs. SCLK duty cycle ............................................................ 10

Figure 21.

ENOB vs. SCLK duty cycle .......................................................... 10

Figure 22.

+/- DNL vs. SCLK ................................................................. 10

Figure 23.

+/- INL vs. SCLK.................................................................. 10

Figure 24.

SNR vs. SCLK ................................................................... 11

Figure 25.

THD vs. SCLK ................................................................... 11

Figure 26.

ENOB vs. SCLK .................................................................. 11

Figure 27.

+/- DNL vs. temperature............................................................. 11

Figure 28.

+/- INL vs. temperature ............................................................. 11

Figure 29.

SNR vs. temperature ............................................................... 11

Figure 30.

THD vs. temperature ............................................................... 12

Figure 31.

ENOB vs. temperature.............................................................. 12

Figure 32.

SNR vs. Fin ..................................................................... 12

Figure 33.

THD vs. Fin ..................................................................... 12

Figure 34.

ENOB vs. Fin .................................................................... 12

Figure 35.

Power dissipation (mW) vs. SCLK ...................................................... 12

Figure 36.

Power dissipation (mW) vs. temperature ................................................. 13

Figure 37.

Functional block diagram ............................................................ 15

Figure 38.

Equivalent input circuit.............................................................. 15

Figure 39.

TSSOP-16 package outline .......................................................... 17

ADC1283

List of figures

DS13932 - Rev 1

page 23/24