AT25SF321B datasheet(39/63 Pages) RENESAS

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DS-AT25SF321B-179 Rev. F

Page 39

2022-06-03

AT25SF321B Datasheet

10.4 Read Security Registers (48h)

The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the

maximum clock frequency specified by fCLK. To read the Security Register, the CS pin must first be asserted and

the opcode of 48h must be clocked into the device. After the opcode has been clocked in, the three address bytes

must be clocked in to specify the starting address location of the first byte to read within the Security Register.

Following the three address bytes, one dummy byte must be clocked into the device before data can be output.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles result in the

Security Register data being output on the SO pin. When the last byte (0003FFh) of the Security Register has

been read, the device continues reading back at the beginning of the register (000000h). No delays are incurred

when wrapping around from the end of the register to the beginning of the register.

Deasserting the CS pin terminates the read operation and puts the SO pin into a high-impedance state. The CS

pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 30. Read Security Registers

Table 10. Security Register Addresses for Read Security Registers Command

Address

A23-A16

A15-A12

A11-A8

A7-A0

Security Register 1

00h

Byte Address

Security Register 2

00h

Byte Address

Security Register 3

00h

Byte Address

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