ST25R3912 datasheet(31/130 Pages) STMICROELECTRONICS

31 / 130 page

DS11794 Rev 9

31/130

ST25R3912

Functional overview

Figure 8. Exchange of signals with microcontroller

MISO output is usually in tristate, it is only driven when output data is available. Due to this

the MOSI and the MISO can be externally shorted to create a bidirectional signal.

During the time the MISO output is in tristate, it is possible to switch on a 10 kΩ pull down by

activating option bits miso_pd1 and miso_pd2 in the IO configuration register 2.

Table 6 provides information on the SPI operation modes. Reading and writing of registers

is possible in any ST25R3912 operation mode. FIFO operations are possible in case en (bit

7 of the Operation control register) is set and Xtal oscillator frequency is stable.

Writing data to addressable registers (Write mode)

Figure 9 and Figure 10 show cases of writing a single byte and writing multiple bytes with

auto-incrementing address. After the SPI operation mode bits, the address of register to be

written is provided. Then one or more data bytes are transferred from the SPI, always from

the MSB to the LSB. The data byte is written in register on falling edge of its last clock. In

case the communication is terminated by putting /SS high before a packet of 8 bits (one

byte) is sent, writing of this register is not performed. In case the register on the defined

address does not exist or it is a read only register no write is performed.

MS42438V2

MOSI

MISO

I/O

MOSI

MISO

MOSI

Separate SPI input and

output signals to MCU

Bidirectional data

IO signal to MCU

Table 6. SPI operation modes

Mode

Pattern (communication bits)

Related data

Mode

Trailer

A0 Data byte (or more bytes in case of

auto-incrementing)

FIFO load

100

0000

One or more bytes of FIFO data

FIFO read

101

1111

Direct command mode

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