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STM32U535NET3QTR bảng dữ liệu(PDF) 239 Page - STMicroelectronics

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DS14217 Rev 1
239/278
STM32U535xx
Electrical characteristics
253
5.3.29
DCMI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 32, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Figure 48. DCMI timing diagram
Table 118. DCMI characteristics(1)
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
-0.4
-
DCMI_PIXCLK
Pixel clock input
-
64
MHz
DPIXEL
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
2
-
ns
th(DATA)
Data hold time
1
-
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC and DCMI_VSYNC input setup times
2
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC and DCMI_VSYNC input hold times
1
-
1. Evaluated by characterization. Not tested in production.
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)



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