VN9D5D20F datasheet(21/96 Pages) STMICROELECTRONICS

21 / 96 page

Figure 9. SPI read operation

SDI

SDO

CSN

(16bit)

Don’t care

(16bit)

Data

MSB

LSB

MSB Address

(8bit)

Global Status Byte

Command Byte

LSB

MSB

GADG311020171215MT

Read and clear status command

The read and clear status operation is used to clear the content of the addressed status register (see

Table 23. RAM memory map). A read and clear status operation with address 0x3Fh clears all Status registers

simultaneously.

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to

determine which register content is read and the payload bits set to 1 into the data byte determine the bits into the

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the

serial clock (SCK). The first byte corresponds to the Global Status byte and the second to the content of the

addressed register.

In order to avoid inconsistency between the Global Status byte and the Status register, the Status register

contents are frozen during SPI communication.

Figure 10. SPI read and clear operation

CSN

SDI

SDO

Global Status byte

MSB

LSB

Data byte

MSB

LSB

Command byte

MSB

Address

LSB

Data byte

MSB

LSB

(16 bits)

(8 bits)

GADG1010171505PS

Read device information

Specific information can be read but not modified during this mode. Accessible data can be seen in Table 1.

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to

determine which information is read whilst the other two data bytes are "don’t care".

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the

serial clock (SCK). The first byte corresponds to the Global Status byte and the second to the content of the

addressed register and the third byte is 0x00.

Note:

ROM is based on the 8-bit registers, then even if 16 bits are returned, only the second byte contains the

addressed ROM register.

VN9D5D20F

SPI protocol

DS12936 - Rev 6

page 21/96

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