STM32U5A5QJI datasheet(88/382 Pages) STMICROELECTRONICS

88 / 382 page

Functional overview

STM32U5Axxx

88/382

DS13543 Rev 1

•

Up to 8 tamper pins for 8 external tamper detection events:

–

Active tamper mode: continuous comparison between tamper output and input to

protect from physical open-short attacks

–

Flexible active tamper I/O management: from 4 meshes (each input associated to

its own exclusive output) to 7 meshes (single output shared for up to 7 tamper

inputs)

–

Passive tampers: ultra-low power edge or level detection with internal pull-up

hardware management

–

Configurable digital filter

•

11 internal tamper events to protect against transient or environmental perturbation

attacks:

–

Backup domain voltage monitoring

–

Temperature monitoring

–

LSE monitoring

–

RTC calendar overflow

–

JTAG/SWD access if RDP different from 0

–

Monotonic counter overflow

–

Cryptographic peripherals fault (RNG, SAES, AES, PKA)

–

Independent watchdog reset when tamper flag is already set

–

3 ADC4 watchdogs

•

Each tamper can be configured in two modes:

–

Hardware mode: immediate erase of secrets on tamper detection, including

backup registers erase

–

Software mode: erase of secrets following a tamper detection launched by

software

•

Any tamper detection can generate a RTC time stamp event.

•

TrustZone support:

–

Tamper secure or nonsecure configuration

–

Backup registers configuration in 3 configurable-size areas:

- 1 read/write secure area

- 1 write secure/read nonsecure area

- 1 read/write nonsecure area

–

Boot secret key (BHK) only usable by secure AES peripheral, stored in backup

registers, protected against read and write access

•

Tamper configuration and backup registers privilege protection

•

Monotonic counter

3.49

Inter-integrated circuit interface (I2C)

The device embeds six I2C. Refer to Table 21 for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

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