851021 datasheet(2/19 Pages) RENESAS

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1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER

REVISION C 11/03/15

851021 DATA SHEET

Pin Description Table

Table 1. Pin Descriptions

Output Driver Current

The 851021 outputs are HCSL differential current dr ive with

the current being set with a resistor from I

REF to ground. Fo r

a single load and a 50

 P.C. board trace, the drive current would

typically be set with a R

REF of 950 which products an IREF of 1.16mA.

The I

REF is multiplied by a current mirror to an output drive of

12*1.16mA or 13.90mA. See Figure 1 for current mirror and output

drive details.

RREF

950

IREF

Figure 1. HCSL Current Mirror and Output Drive

Number

Name

Type

Description

1, 2

Q3, nQ3

Output

Differential output pair. Differential HCSL interface levels.

3, 9, 14, 21, 24, 25, 29,

35, 40, 46, 52, 57, 62

VDD

Power

Positive supply pins.

4, 5

Q4, nQ4

Output

Differential output pair. Differential HCSL interface levels.

6, 17, 32, 43, 49

GND

Power

Power supply ground.

7, 8

Q5, nQ5

Output

Differential output pair. Differential HCSL interface levels.

10, 11

Q6, nQ6

Output

Differential output pair. Differential HCSL interface levels.

12, 13

Q7, nQ7

Output

Differential output pair. Differential HCSL interface levels.

15, 16

Q8, nQ8

Output

Differential output pair. Differential HCSL interface levels.

RREF

Input

External fixed precision resistor (950

) from this pin to ground provides a reference

current used for differential current-mode Qx, nQx clock outputs.

19, 20

Q9, nQ9

Output

Differential output pair. Differential HCSL interface levels.

22, 23

Q10, nQ10

Output

Differential output pair. Differential HCSL interface levels.

unused

No connect.

27, 28

Q11, nQ11

Output

Differential output pair. Differential HCSL interface levels.

30, 31

Q12, nQ12

Output

Differential output pair. Differential HCSL interface levels.

33, 34

Q13, nQ13

Output

Differential output pair. Differential HCSL interface levels.

36, 37

Q14, nQ14

Output

Differential output pair. Differential HCSL interface levels.

38. 39

Q15, nQ15

Output

Differential output pair. Differential HCSL interface levels.

41, 42

Q16, nQ16

Output

Differential output pair. Differential HCSL interface levels.

44, 45

Q17, nQ17

Output

Differential output pair. Differential HCSL interface levels.

47, 48

Q18, nQ18

Output

Differential output pair. Differential HCSL interface levels.

CLK

Input

Non-inverting differential input.

nCLK

Input

Inverting differential clock input.

53, 54

Q19, nQ19

Output

Differential output pair. Differential HCSL interface levels.

55, 56

Q20, nQ20

Output

Differential output pair. Differential HCSL interface levels.

58, 59

Q0, nQ0

Output

Differential output pair. Differential HCSL interface levels.

60, 61

Q1, nQ1

Output

Differential output pair. Differential HCSL interface levels.

63, 64

Q2, nQ2

Output

Differential output pair. Differential HCSL interface levels.

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