Preliminary Technical Data

Rev. PrA 15-Nov-04| Page 21 of 27

FINE GAIN REGISTER

The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC

channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in

Table 16 and

Table 17.

Table 16. Programming AD5764 Fine Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15 …. DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

0

DAC Address

Don’t Care

FG5

FG4

FG3

FG2

FG1

FG0

Table 17. Fine Gain Register Options

Gain Adjustment

FG5

FG4

FG3

FG2

FG1

FG0

+31 LSBs

0

1

1

1

1

1

+30 LSBs

0

1

1

1

1

0

-

-

-

-

-

-

No Adjustment

0

0

0

0

0

0

-

-

-

-

-

-

-31 LSBs

1

0

0

0

0

1

-32 LSBs

1

0

0

0

0

0

OFFSET REGISTER

The Offset Register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The Offset Register is an 8-bit register and allows the user to adjust the offset of each channel

by – 15.875 LSBs to + 16 LSBs in steps of 1/8 LSB as shown in Table 18 and Table 19.

Table 18. Programming the Offset Register

REG2

REG1

REG0

A2

A1

A0

DB15 …. DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

DAC Address

Don’t Care

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

Table 19. Offset Register options

Offset Adjustment

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

+15.875 LSBs

0

1

1

1

1

1

1

1

+16.5 LSBs

0

1

1

1

1

1

1

0

-

-

-

-

-

-

-

-

No Adjustment

0

0

0

0

0

0

0

0

-

-

-

-

-

-

-

-

-15.875 LSBs

1

0

0

0

0

0

0

1

-16 LSBs

1

0

0

0

0

0

0

0