82P33741 datasheet(23/59 Pages) RENESAS

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September 15, 2017

82P33741 Datasheet

3.1.6

APLL3

The APLL3 is provided for a better jitter and wander performance of

the device differential output clocks OUT10 and OUT11.

APLL3 supports 3 clock modes: SONET, Ethernet, and Ethernet

LAN. The base frequency for the 3 clock modes are 622.08 MHz,

625 MHz, and 644.53125 MHz respectively. The clock mode selected is

determined by the crystal used for the APLL.

The APLL uses a crystal to generate the respective mode’s base fre-

quency. The supported crystal frequencies are 24.8832 MHz (SONET),

25 MHz (Ethernet) and 25.78125 MHz (Ethernet LAN). The APLL sup-

ports up to two crystal connections, allowing the APLL to support up to

two mode’s base frequencies.

The input of both APLL3 can be derived from one of the DPLL1 or

DPLL2 outputs by configuring internal registers as described in

Table 10. The bandwidth for APLL3 is set to greater 30 Hz (typical),

therefore the bandwidth of DPLL1 or the DPLL2 that is connected to

APLL3 should be set to 18 Hz.

3.1.6.1

External Crystals

Suggestions for crystal options and best matching to APR require-

ments, crystal tolerance considerations and budgets, component place-

ment and crystal wiring to achieve minimum capacity are fully detailed in

IDT AN-861, “Recommended Crystals and Layout Guidelines for IDT’s

VCXO-based Synchronization PLLs.

Table 10: APLL3 input selection

Crystal

APLL3 Input

APLL3_mux_cnfg[3:0] APLL3_div1_cnfg[7:0] APLL3_div2_cnfg[26:0] APLL3_pd_sel[14:0]

APLL3_pd_sel[14:0]

24.88320

8100 Hz from DPLL1

0x04

0x01

0x000012BF

0x0001

0x0C00

24.88320

8100 Hz from DPLL2

0x0C

0x01

0x000012BF

0x0001

0x0C00

25.00000

8000 Hz from DPLL1

0x04

0x01

0x000012FB

0x0001

0x0C35

25.00000

8000 Hz from DPLL2

0x0C

0x01

0x000012FB

0x0001

0x0C35

25.78125 7812.5 Hz from DPLL1

0x03

0x01

0x0000063F

0x0001

0x0CE4

25.78125 7812.5 Hz from DPLL2

0x0B

0x01

0x0000063F

0x0001

0x0CE4

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