ADC0832CIWM datasheet(15/33 Pages) NSC

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Functional Description (Continued)

TABLE 6. MUX Addressing: ADC0832

Single-Ended MUX Mode

MUX Address

Channel #

SGL/

ODD/

DIF

SIGN

COM is internally tied to A GND

TABLE 7. MUX Addressing: ADC0832

Differential MUX Mode

MUX Address

Channel #

SGL/

ODD/

DIF

SIGN

−

Since the input configuration is under software control, it can

be modified, as required, at each conversion. A channel can

be treated as a single-ended, ground referenced input for

one conversion; then it can be reconfigured as part of a

differential channel for another conversion. Figure 1 illus-

trates the input flexibility which can be achieved.

The analog input voltages for each channel can range from

50 mV below ground to 50 mV above V

CC (typically 5V)

without degrading conversion accuracy.

2.0 THE DIGITAL INTERFACE

A most important characteristic of these converters is their

serial data link with the controlling processor. Using a serial

communication format offers two very significant system

improvements; it allows more function to be included in the

converter package with no increase in package size and it

can eliminate the transmission of low level analog signals by

locating the converter right at the analog sensor; transmitting

highly noise immune digital data back to the host processor.

To understand the operation of these converters it is best to

refer to the Timing Diagrams and Functional Block Diagram

and to follow a complete conversion sequence. For clarity a

separate diagram is shown of each device.

1. A conversion is initiated by first pulling the CS (chip select)

line low. This line must be held low for the entire conversion.

The converter is now waiting for a start bit and its MUX

assignment word.

2. A clock is then generated by the processor (if not provided

continuously) and output to the A/D clock input.

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