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ZL40293 bảng dữ liệu(PDF) 13 Page - Microsemi Corporation

tên linh kiện ZL40293
Giải thích chi tiết về linh kiện  20-Output PCIe Gen 1, 2 ,3, 4 and 5 Buffer with Ultra-Low Additive Jitter
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nhà sản xuất  MICROSEMI [Microsemi Corporation]
Trang chủ  http://www.microsemi.com
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Data Sheet
ZL40293
ZL40293
March 2019
© 2019 Microsemi Corporation
13
Programming via SMBus
The address selection is done via SA_0 and SA_1 tri-level hardware pins, which select the appropriate address for
the device. The two tri-level input pins that can configure the ZL40293 to nine different addresses (refer to Table 15
for VIL_Tri, VIM_Tri, VIH_Tri signal level).
Table 4 SMBus Address Table
SA_1
SA_0
SMBus Address
L
L
D8
L
M
DA
L
H
DE
M
L
C2
M
M
C4
M
H
C6
H
L
CA
H
M
CC
H
H
CE
SMBus Byte Read/Write
Reading or writing a register in a SMBus slave device in byte mode always involves specifying the register number.
Read. The standard byte read is as shown in Figure 11. It is an extension of the byte write. The write start condition is
repeated then the slave device starts sending data and the master acknowledges it until the last byte is sent. The
master terminates the transfer with a NAK then a stop condition. For byte operation, the 2*7th bit of the command byte
must be set. For block operations, the 2*7th bit must be reset. If the bit is not set, the next byte must be the byte
transfer count.
Figure 11.
SMBus Byte Read
T
Slave
Command
r
Slave
A
N
P
Wr
Rd
StarT
Condition
Command
Register #
to read
2*7 bit = 1
repeat starT
Acknowledge
Not ack
stoP
Condition
Master
drive Bus
Slave
drive Bus
1
7
1
1
8
1
1
8
1
1
8
1
1
A
A
Data Byte 0



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