FN2975 Rev 2.00

Page 1 of 8

Aug 25, 2015

FN2975

Rev 2.00

Aug 25, 2015

82C82

CMOS Octal Latching Bus Driver

DATASHEET

Features

• Full Eight-Bit Parallel Latching Buffer

• Bipolar 8282 Compatible

• Three-State Noninverting Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.

• Gated Inputs:

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation. . . . . . . . . . . . . . . .ICCSB = 10

A

• Operating Temperature Ranges

- C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC

- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

Description

The Intersil 82C82 is a high performance CMOS Octal

Latching Buffer manufactured using a self-aligned silicon

gate CMOS process (Scaled SAJI IV). The 82C82 provides

an eight-bit parallel latch/buffer in a 20 pin package. The

active high strobe (STB) input allows transparent transfer of

data and latches data on the negative transition of this

signal. The active low output enable (OE) permits simple

interface to state-of-the-art microprocessor systems.

Pinouts

82C82 (PDIP, CERDIP)

TOP VIEW

82C82 (PLCC, CLCC)

TOP VIEW

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

DI0

DI1

DI2

DI3

DI4

DI5

DI7

DI6

OE

GND

VCC

DO1

DO2

DO3

DO0

DO4

DO5

DO6

DO7

STB

19

3

2

20

1

15

16

17

18

14

9

10

11

12

13

4

5

6

7

8

DI4

DI5

DI6

DI7

DI3

DO2

DO3

DO4

DO5

DO1

NO

LO

NG

ER

AV

AI

LA

BL

E O

R

SU

PP

OR

TE

D

TRUTH TABLE

STB

OE

DI

DO

XH

X

Hi-Z

HL

L

L

HL

H

H



LX

†

H

= Logic One

L

= Logic Zero

X

= Don’t Care

†

= Latched to Value of Last

Data

Hi-Z = High Impedance



= Neg. Transition

PIN NAMES

PIN

DESCRIPTION

DI0-DI7

Data Input Pins

DO0-DO7

Data Output Pins

STB

Active High Strobe

OE

Active Low Output

Enable