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74LVC86AD bảng dữ liệu(PDF) 4 Page - NXP Semiconductors

tên linh kiện 74LVC86AD
Giải thích chi tiết về linh kiện  Quad 2-input exclusive OR gate
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nhà sản xuất  PHILIPS [NXP Semiconductors]
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74LVC86AD bảng dữ liệu(HTML) 4 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC86A
Quad 2-input exclusive OR gate
1998 Apr 28
4
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°C to +85°C
UNIT
MIN
TYP1
MAX
V
HIGH level Input voltage
VCC = 1.2V
VCC
V
VIH
HIGH level Input voltage
VCC = 2.7 to 3.6V
2.0
V
V
LOW level Input voltage
VCC = 1.2V
GND
V
VIL
LOW level Input voltage
VCC = 2.7 to 3.6V
0.8
V
VCC = 2.7V; VI = VIH or VIL;IO = –12mA
VCC*0.5
VO
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL;IO = –100µA
VCC*0.2
VCC
V
VOH
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC*0.6
V
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC*0.8
VCC = 2.7V; VI = VIH or VIL;IO = 12mA
0.40
VOL
LOW level output voltage
VCC = 3.0V; VI = VIH or VIL;IO = 100µA
0.20
V
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
0.55
I
Input leakage current
VCC =3 6V; V = 5 5V or GND
"01
"5
µA
II
Input leakage current
VCC = 3.6V; VI = 5.5V or GND
"0.1
"5
µA
ICC
Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
0.1
10
µA
∆ICC
Additional quiescent supply current
per input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
5
500
µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = –40_C to +85_C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
VCC = 2.7V
VCC = 1.2V
UNIT
MIN
TYP1
MAX
MIN
TYP1
MAX
TYP
tPHL/
tPLH
Propagation delay
nA, nB to nY
Figures 1, 2
1.5
3.0
5
1.5
3.4
5.8
11
ns
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V
VM = 0.5 S VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
nA, nB INPUT
GND
VOH
nY OUTPUT
VOL
VM
tPHL
tPLH
VM
SV00377
Figure 1. Input (nA, nB) to output (nY) propagation delays
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
D.U.T.
VO
CL
50pF
S1
2
< VCC
Open
GND
500
Ω
500
Ω
VCC
VI
t 2.7V
VCC
2.7V – 3.6V
2.7V
Test
S1
tPLH/tPHL
Open
VCC
SY00077
Figure 2. Load circuitry for switching times.



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