Dual D-type flip-flop with set and reset;

positive-edge trigger

Philips Semiconductors

Product Specification

74LVC74A

1998 Jun 17

6

AC WAVEFORMS

output load.

SV00489

VM

nD INPUT

nCP INPUT

nQ OUTPUT

nQ OUTPUT

VM

VM

VM

t su

t su

1/f max

t h

th

t PHL

t PHL

t PLH

t PLH

tW

GND

GND

VI

VI

VOL

VOL

VOH

VOH

NOTE: The shaded areas indicate when the inputis permitted to change for predictable

output performance.

Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,

clock pulse width, nD to nCP set-up times,

the nCP to nD hold times, output transition times

and maximum clock pulse frequency.

SV00490

VM

nCP INPUT

nS D INPUT

nR D INPUT

nQ OUTPUT

nQ OUTPUT

VM

VM

VM

trem

tPHL

tPLH

tW

tW

VM

tPHL

tPLH

GND

GND

GND

VI

VI

VI

VOL

VOL

VOH

VOH

propagation delays, the set and reset pulse widths

and the nRD to nCP removal time.

TEST CIRCUIT

SWITCH POSITION

PULSE

GENERATOR

RT

VI

D.U.T.

VO

CL

VCC

500

Ω

Open

GND

< 2.7V

TEST

Open

2.7V

2.7–3.6V

50pF

500

Ω

SV00903

Figure 3. Load circuitry for switching times.