9DB202 Data Sheet

©2016 Integrated Device Technology, Inc

Revision B March 11, 2016

2

TABLE 2. PIN CHARACTERISTICS

TABLE 3A. RATIO OF OUTPUT FREQUENCY TO

INPUT FREQUENCY FUNCTION TABLE, FS0

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

Inputs

Outputs

FS0

PCIEX0

0

5/4

11

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

PLL_BW

Input

Pullup

Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.

2

CLK

Input

Pulldown Non-inverting differential clock input.

3

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input. V

DD

/2 default when left floating.

4

FS0

Input

Pullup

Frequency select pin. LVCMOS/LVTTL interface levels.

5, 9, 12, 16

V

DD

Power

Core supply pins.

6, 15

GND

Power

Power supply ground.

7, 8

PCIEXT0,

PCIEXC0

Output

Differential output pairs. HCSL interface levels.

10, 11

nOE0, nOE1

Input

Pulldown

Output enable. When HIGH, forces outputs to HiZ state.

When LOW, enables outputs. LVCMOS/LVTTL interface levels.

13, 14

PCIEXC1,

PCIEXT1

Output

Differential output pairs. HCSL interface levels.

17

FS1

Input

Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.

18

IREF

Input

A fixed precision resistor (475

Ω) from this pin to ground provides a refer-

ence current used for differential current-mode PCIEX clock outputs.

19

BYPASS

Power

Pulldown

BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.

LVCMOS/LVTTL interface levels.

20

V

DDA

Power

Analog supply pin. Requires 24

Ω series resistor.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 3B. RATIO OF OUTPUT FREQUENCY TO

INPUT FREQUENCY FUNCTION TABLE, FS1

Inputs

Outputs

FS1

PCIEX1

01

1

5/4

TABLE 3D. OUTPUT ENABLE

FUNCTION TABLE, NOE0

Inputs

Outputs

nOE0

PCIEX0

0

Enabled

1

HiZ

TABLE 3E. OUTPUT ENABLE

FUNCTION TABLE, NOE1

Inputs

Outputs

nOE1

PCIEX1

0

Enabled

1

HiZ

TABLE 3F. PLL BANDWIDTH TABLE

Inputs

Bandwidth

PLL_BW

0

500kHz

1

1MHz

TABLE 3C. BYPASS TABLE

Inputs

Mode

BYPASS

0

PLL Mode

1

Bypass Mode

(output = inputs)