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M5CAARCH-RM/D bảng dữ liệu(PDF) 58 Page - NXP Semiconductors

tên linh kiện M5CAARCH-RM/D
Giải thích chi tiết về linh kiện  C-5e NETWORK PROCESSOR SILICON REVISION A1
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M5CAARCH-RM/D bảng dữ liệu(HTML) 58 Page - NXP Semiconductors

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58
CHAPTER 2: SIGNAL DESCRIPTIONS
C
Test Signals
Test signals are described in Table 30.
During JTAG, SCLK and SCLKX must remain as differential inputs.
No Connection Pins
No connection pins are listed in Table 31.
Table 30 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
JTCK
C15
1
LVTTL
I
PD
Test Clock
JTMS
A14
1
LVTTL
I
PD
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
JTRSTX†
A12
1
LVTTL
I
PD
Test Reset (low active)
JTDI†
B14
1
LVTTL
I
PD
Test Data In
JTDO
A13
1
LVTTL
O
Test Data Out
JHIGHZ
B13
1
LVTTL
I
PD
Turns off all output drivers when High
JCLKBYP
C14
1
LVTTL
I
PD
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
JSE
D15
1
LVTTL
I
PD
Scan Enable. High enables scan test.
JS00-JS05
D14, A16, D13, C12, A15, B12
6
LVTTL
O
Scan Out Pins
TOTAL PINS
14
Table 31 No Connection Pins
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
NC3 - NC5
B11, A11, A18
3
nc
I
PD/O
Reserved for future functionality
TOTAL PINS
3
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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