VC16373ADL datasheet(6/10 Pages) PHILIPS

6 / 10 page

Philips Semiconductors

Product specification

74LVC16373A/

74LVCH16373A

16-bit D-type transparent latch with 5 Volt tolerant

inputs/outputs (3-State)

1998 Mar 17

DC ELECTRICAL CHARACTERISTICS (Continued)

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40

°C to +85°C

UNIT

MIN

TYP1

MAX

IBHL

Bus hold LOW sustaining current

VCC = 3.0V; VI = 0.8V2, 3, 4

µA

IBHH

Bus hold HIGH sustaining current

VCC = 3.0V; VI = 2.0V2, 3, 4

–75

µA

IBHLO

Bus hold LOW overdrive current

VCC = 3.6V2, 3, 5

500

µA

IBHHO

Bus hold HIGH overdrive current

VCC = 3.6V2, 3, 5

–500

µA

NOTES:

1. All typical values are at VCC = 3.3V and Tamb = 25°C.

2. Valid for data inputs of bus hold parts (LVCH16-A) only.

3. For data inputs only, control inputs do not have a bus hold circuit.

4. The specified sustaining current at the data input holds the input below the specified VI level.

5. The specified overdrive current at the data input forces the data input to the opposite logic input state.

6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal.

AC CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.

LIMITS

SYMBOL

PARAMETER

WAVEFORM

VCC = 3.3V ±0.3V

VCC = 2.7V

VCC = 1.2V

UNIT

MIN

TYP1

MAX

MIN

MAX

TYP

tPHL

tPLH

Propagation delay

Dn to Qn

1, 5

1.5

3.0

4.7

1.5

5.7

tPHL

tPLH

Propagation delay

LE to Qn

2, 5

1.5

3.4

4.8

1.5

5.8

tPZH

tPZL

3-State output enable time

OE to Qn

4, 5

1.5

3.5

5.5

1.5

6.5

tPHZ

tPLZ

3-State output disable time

OE to Qn

4, 5

1.5

3.9

5.4

1.5

6.4

LE pulse width HIGH

2.0

–

tsu

Set-up time Dn to LE

1.7

–0.1

–

1.7

–

Hold time Dn to LE

1.2

0.1

–

1.2

–

NOTE:

1. All typical values are at VCC = 3.3V and Tamb = 25°C.

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.

VOL and VOH are the typical output voltage drop that occur with the output load.

VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V

VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V

SW00070

Dn INPUT

tPHL

tPLH

VOL

GND

VOH

Qn OUTPUT

Waveform 1. Input (Dn) to output (Qn) propagation delays

tPHL

tPLH

LE INPUT

Qn OUTPUT

SW00071

GND

VOH

VOL

Waveform 2. Latch enable input (LE) pulse width, the latch

enable input to output (Qn) propagation delays

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