74LVC109D datasheet(6/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

74LVC109

Dual JK flip-flop with set and reset; positive-edge trigger

1998 Apr 28

AC WAVEFORMS

VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V.

VOL and VOH are the typical output voltage drop that occur with the output load.

The shaded areas indicate when the input is permitted to change

for predictable output performance.

SV00522

1/f max

t h

t PLH

t PHL

t PLH

t PHL

t W

t su

nJ, nK

INPUT

nCP

INPUT

OUTPUT

GND

VOH

VOL

OUTPUT

Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,

the clock pulse width, the nJ and nK to nCP set-up,

the nCP to nJ, nK hold times

and the maximum clock pulse frequency.

SV00523

tPLH

tPHL

trem

nSD

INPUT

nRD

INPUT

nCP

INPUT

OUTPUT

VOH

VOL

GND

OUTPUT

trem

tPLH

tPHL

Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)

propagation delays, the set and reset pulse widths

and the nRD, nSD to nCP removal time.

TEST CIRCUIT

NEGATIVE

PULSE

10%

90%

POSITIVE

PULSE

90%

10%

tTHL (tf)

tTLH (tr)tTHL (tf)

tTLH (tr)

VM = 1.5V

Input Pulse Definition

SWITCH POSITION

PULSE

GENERATOR

D.U.T.

Vcc

Test Circuit for Outputs

Open

GND

DEFINITIONS

VCC

< 2.7V

2.7–3.6V

VCC

2.7V

TEST

tPLH/tPHL

Open

≥ 4.5 V

VCC

RL = Load resistor; see AC CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance:

See AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of

pulse generators.

SV00904

< VCC

Figure 3. Load circuitry for switching times.

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